Texas Instruments Placement Papers: Test Pattern and Syllabus

Texas Instruments runs three parallel campus profiles (Analog Design, Digital Design, and Embedded Software), and the online assessment changes entirely depending on which one you sit.

That single structural choice makes TI recruitment different from most mass-recruiter drives. There is no generic aptitude-plus-coding test that works the same way for every student. ECE and EEE students who have genuinely studied their core subjects have an edge here that broader-based drives rarely reward.

How TI’s Campus Selection Works

The recruitment process has three stages, applied consistently across campus drives in India:

• Online Assessment (OA): A common aptitude section followed by a profile-specific technical section. First round of elimination.
• Technical Interview: One or two rounds of core-subject questioning, with substantial time spent on the candidate’s CV and projects.
• HR Interview: A standard round covering motivation, career goals, and cultural fit. Reaching this stage typically means the offer is close.

For off-campus hiring, TI screens on resume and does not run the same OA format. The rest of this article covers the campus process.

Online Assessment: Structure and Format

The OA has two parts: a common aptitude section that every candidate sits, and a profile-specific technical section. Candidates choose their profile (or two profiles, at most) at registration.

Section	Questions	Time	Profiles
Aptitude	~20	~20 min	All profiles (common)
Analog Design Technical	~20	~30 min	Analog profile only
Digital Design Technical	~20	~30 min	Digital profile only
Embedded Software Technical	~20	~30 min	Embedded Software profile only

A candidate who registers for two profiles (say, Analog and Digital) sits all three sections: the common aptitude plus both technical sections, back to back.

Negative marking applies to the aptitude section. Based on placement accounts from IIT Kharagpur’s 2024 cohort, clearing 11–12 correct answers out of ~20 is typically enough to pass the aptitude cut-off. The implication: do not guess on questions where you are not confident. TI’s aptitude is not a volume test.

The difficulty level is moderate. Most questions can be solved in 60–90 seconds with a clean approach. Accuracy, not raw speed, is the deciding factor.

Technical sections are harder to shortcut. The questions in both Analog and Digital are weighted toward applied concepts, not rote definitions. Correct setup and fast pattern recognition matter more than memorised formulas.

Syllabus by Profile

Aptitude Section (All Profiles)

The aptitude section applies to every candidate regardless of profile chosen. Topics:

• Time, Speed, and Distance
• Time and Work
• Probability
• Permutations and Combinations
• Basic Number Theory (divisibility, factors, LCM/HCF)
• Linear Equations and Arithmetic
• Syllogisms and basic logical patterns

Analog Design Profile

The Analog Design section tests circuit intuition at an intermediate-to-advanced level. TI specifically expects candidates to derive bode plots, transient responses, and initial or final states from inspection, without writing differential equations from scratch.

Network Theory (highest weight):

• First-order and second-order RC and RL circuits — step and pulse response by intuition
• Finding poles and zeros by inspection; drawing bode plots from first principles
• Charge sharing between capacitors with and without initial conditions
• Filter identification (low-pass, high-pass, band-pass, band-stop, all-pass)

Analog Circuits:

• Standard op-amp configurations: inverting, non-inverting, adder, subtractor, differentiator, integrator
• Op-amp non-idealities: finite open-loop gain, finite bandwidth, slew rate, input/output resistance, offset voltage
• Barkhausen criterion and positive-feedback oscillator circuits (RC phase shift, Wien bridge, multivibrators)
• Regulators and feedback identification

Microelectronics:

• I-V characteristics and operating regions for diodes, BJTs, and MOSFETs
• Gain of common-source, common-gate, common-drain, cascode, and cascade amplifiers — by intuition without small-signal models
• Current mirror architectures (simple, cascode, Wilson, wide-swing) and headroom considerations
• Differential amplifier with passive and active load; differential gain, common-mode gain, CMRR
• OTA architectures (5T, telescopic, folded cascode) — DC gain, poles, zeros, UGB, phase margin

Control Systems:

• Gain margin, phase margin, gain crossover frequency, phase crossover frequency
• Stability analysis from bode plots

Signals and Systems (secondary weight):

• LTI system basics, convolution, DTFT, DFT

Digital Design Profile

The Digital Design section covers the standard ECE/EEE digital curriculum, with computer architecture added.

• Boolean algebra and simplification (K-maps, algebraic methods)
• Combinational logic: MUX/DEMUX, encoders, decoders, half-adder/full-adder
• Sequential logic: latches, flip-flops, counters (synchronous and asynchronous), shift registers
• Finite State Machines (Moore and Mealy)
• Static timing analysis: setup time, hold time, clock-to-Q delay
• Memory organisation: cache hierarchy, direct-mapped and set-associative mapping, write policies
• Computer architecture basics: instruction formats, addressing modes, pipelining fundamentals
• Verilog: basic syntax, blocking and non-blocking assignments, combinational and sequential modules
• Digital signal processing concepts: sampling, Nyquist theorem, basic filter types

Embedded Software Profile

The Embedded Software section is closer to a software-engineering test with a hardware-awareness layer. Per the IIT Kharagpur 2025 internship account, the topics that appeared:

• Data Structures and Algorithms: arrays, linked lists, trees, sorting, searching — standard competitive-programming repertoire
• C and C++ fundamentals: pointer arithmetic, memory allocation (malloc/free), dynamic arrays, syntax-based MCQs
• Object-Oriented Programming: classes, inheritance, polymorphism, virtual functions
• Operating Systems: process scheduling, memory management, inter-process communication, deadlock conditions
• Computer Networks: OSI model, TCP/IP, socket programming basics
• DBMS: normalisation, SQL fundamentals, transaction concepts
• Bit Manipulation and Logic Gates: operations applied to device-driver-level problems; NAND/NOR gate equivalences

The framing throughout is “bit manipulation applied to real embedded contexts.” Candidates who have written bare-metal C for microcontrollers or firmware projects find the questions familiar from first principles.

Sample Question Types from TI Papers

The following question types recur across placement accounts and older TI papers. Where the question has a verifiable answer, the answer is noted. Questions that require circuit diagrams (diode biasing, multi-transistor amplifier stages) are topic-listed below but not reproduced. Work through Razavi’s problem sets for those.

Aptitude:

• Palindrome date puzzles in MMDDYYYY format. For example, October 2, 2001 written as 10022001 is a palindrome; the question asks for the previous or next palindrome date, which requires systematic digit analysis of valid month/day/year combinations.
• Clock-hand meeting intervals: the minute and hour hands of a clock meet 11 times every 12 hours, with consecutive meetings approximately 65 minutes and 27 seconds apart.
• Relative motion problems involving two objects moving toward each other and a third object covering distance in the time before they collide.

Digital Design:

• Universal logic sets: AND plus OR together do not form a universal logic set because NOT cannot be derived from them alone. NAND, NOR, a 2-to-1 MUX, and XOR plus NOT each independently form universal sets.
• Logic minimisation using NAND gates; NAND-NAND two-level implementations of sum-of-products expressions such as Y = AB + CD + EF.
• Oscillator criterion: for a feedback system to sustain oscillation, the Barkhausen criterion requires the total loop-gain phase shift to be 360 degrees and the loop gain magnitude to equal 1. The correct answer to the multiple-choice version is 360 degrees, not 90 or 270.

Computer Architecture:

• Interrupt latency is defined as the time between the assertion of an interrupt request and the start of the interrupt service routine (ISR), not its completion.
• Average memory access time (AMAT): for a two-level memory system where M1 has an access time of 2 ns and a hit probability of 0.97, and the miss penalty is 100 ns, the AMAT is 5 ns (2 + 0.03 × 100).

Analog:

• RC circuit transient analysis: given a first-order circuit with a step input, state the initial value, final value, and time constant by inspection — no differential equation needed
• Op-amp feedback polarity identification: given a multi-feedback circuit, identify whether positive or negative feedback dominates and what the resulting circuit behaviour is

Interview Rounds and How to Prepare

Technical Interview

The technical interview runs one to two rounds, conducted online, each roughly an hour. Based on placement reports from IIT Kharagpur’s 2024 cycle, the structure is consistent: the interviewer opens with the candidate’s projects and stays there for 20 to 40 minutes before moving to subject-matter questions.

For the analog profile, project questions go deep: ADC design decisions, comparator topology choices, power consumption trade-offs in a specific block, and explanation of a published algorithm referenced in the BTP or MTP report. The message from multiple placement accounts is consistent: do not include projects you cannot defend to component-level detail.

For analog design, Siemens also runs a comparable circuit-theory OA with project-driven interviews. The Siemens campus test pattern is worth reviewing as a second data point for ECE students preparing core-profile drives.

After projects, the interviewer shifts to core-subject problems. For analog: RC circuit bode plots and transient responses by inspection, current mirror headroom, opamp bandwidth limitations. For embedded software: OS scheduling algorithms, C pointer arithmetic, dynamic memory, bit manipulation coding problems on a shared screen.

HR Interview

Standard round. Questions cover motivation for joining TI (semiconductor and IC design interest is a genuine answer and works better than a generic one), long-term career direction, and standard behavioural prompts. Reaching the HR round at TI typically means the technical bar has been cleared; the HR round is a fit check, not a second elimination gate.

Preparation by Profile

For the analog profile, two foundational texts cover the OA and most of the interview: Razavi’s Microelectronics and Neaman’s Microelectronics. The intuitive RC circuit analysis that TI specifically rewards is best developed through problem sets, not reading. Work through Chembiyan T’s RC circuit YouTube playlist and the IIT Kanpur SSCD open courseware after each concept chapter. The RLC Analog blog on cracking TI’s analog assessment provides a topic-by-topic checklist that aligns with reported question patterns.

For the digital profile, Mano’s Digital Logic and Computer Design covers combinational and sequential logic through counters and FSMs. For computer architecture and cache hierarchy, Patterson and Hennessy’s Computer Organisation and Design is the standard reference.

For the embedded software profile, the preparation path is closer to competitive programming than to core ECE prep. LeetCode and Codeforces handle DSA; GeeksforGeeks covers OS, CN, and DBMS fundamentals; writing actual bare-metal C code (even for a small STM32 or Arduino project) gives the device-driver framing that TI’s embedded questions assume.

On Eligibility

Campus shortlisting is CV-based. The standard CGPA threshold is 7.0, per the IIT Kharagpur 2025 internship account. Branch eligibility covers ECE, EEE, and Instrumentation for the Analog and Digital profiles; the Embedded Software profile typically extends to CSE as well. Check with your college placement cell for cycle-specific eligibility conditions.

TI hires primarily for its Bengaluru campus (the India Design Centre, one of TI’s largest R&D sites globally), with some roles in Hyderabad and Pune.

High-CGPA ECE and EEE students targeting multiple core-profile roles should compare TI’s digital section with the D.E. Shaw campus test pattern, which draws from a similar pool of quant-and-systems candidates at premier institutions.

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