Texas Instruments Interview Questions: Analog and Digital Profiles

Texas Instruments technical interviews follow a consistent pattern: the interviewer spends the first 20 to 30 minutes on your CV and projects before shifting to core-subject questions.

This article covers the actual interview questions for analog and digital profiles. For the online assessment structure, eligibility criteria, and profile-wise syllabus, see the companion guide Texas Instruments Placement Papers: Test Pattern and Syllabus. The two articles work together: the test-pattern article tells you what to study, this one tells you what the interviewer will ask next.

What the TI Technical Interview Looks Like

The selection process has two to three interview rounds after the online assessment. Based on placement accounts from IIT Kharagpur’s 2024 campus cycle, the structure is consistent across profiles:

• The interviewer opens with your CV and stays on one project for 20 to 30 minutes.
• Questions go component-level deep: comparator topology choices, power consumption trade-offs, or why a specific ADC architecture was used in a BTP project.
• Only after projects does the interviewer shift to textbook circuit-theory questions.
• The second technical round, when present, repeats the same pattern with deeper subject questions.

The message across placement reports is direct: do not list projects you cannot defend to component-level detail. A three-line VLSI project description that you cannot explain beyond the block diagram will consume the full interview time.

Both profiles share a common principle. TI does not expect you to solve circuit equations from scratch in an interview. The expectation is Bode-plot reasoning, initial-condition identification, and stability analysis by inspection. That applies to analog RC circuits and digital timing diagrams equally.

Analog Design Profile Interview Questions

RC, RL, and LC Circuits

• Q: Find the time constant of an RC circuit with R = 10 kΩ and C = 100 nF.

• Approach: τ = RC = 10 × 10³ × 100 × 10⁻⁹ = 1 ms. State the initial condition (voltage across capacitor at t=0), the final condition (steady-state voltage), and sketch the exponential response.

• Q: Derive the Bode plot for G(s) = ω/(s + ω) by inspection.

• Approach: Rewrite as G(s) = 1/(1 + s/ω). This is a first-order low-pass filter. DC gain is 0 dB. Pole at s = -ω sets the break frequency at ω rad/s. Above ω, the magnitude rolls off at -20 dB/decade. Phase starts at 0°, passes through -45° at the pole frequency, and approaches -90° at high frequency. Sketch straight-line Bode approximation without writing the differential equation.

• Q: A capacitor C charged to V₀ is connected in parallel to an identical uncharged capacitor. What is the final voltage?

• Approach: Apply charge conservation. Initial charge Q = C·V₀. After connection, total capacitance = 2C. Final voltage = Q / 2C = V₀/2. TI commonly asks a follow-up: where does the energy go? Answer: energy dissipated in the resistance of the connecting wire (even if not explicitly drawn), regardless of wire resistance value.

Operational Amplifiers

• Q: Explain virtual ground in an inverting amplifier configuration.

• Approach: With ideal negative feedback and infinite op-amp gain, any non-zero differential input would drive the output to ±∞. The feedback network forces V⁻ to match V⁺, which is tied to ground. So V⁻ ≈ 0 V. This is virtual ground: the node is at 0 V potential but draws no current into the op-amp input terminal.

• Q: Design an inverting amplifier with a gain of -10 using R₁ = 1 kΩ. What is R₂?

• Approach: Closed-loop gain = -R₂/R₁ = -10. Therefore R₂ = 10 kΩ. Add a compensation resistor R₃ = R₁ ∥ R₂ = 909 Ω at the non-inverting input to cancel the offset from input bias currents.

• Q: What is the slew rate of an op-amp and why does it matter?

• Approach: Slew rate is the maximum rate of change of output voltage, in V/μs. It sets the largest undistorted sinusoidal amplitude at a given frequency: SR = 2πf·V_peak. If the input drives the output faster than the slew rate allows, the output clips into a triangular waveform regardless of gain setting.

• Q: What is the Barkhausen criterion for a stable oscillator?

• Approach: Two conditions must hold simultaneously. First, the magnitude of the loop gain must equal exactly 1 (|Aβ| = 1). Second, the total phase shift around the loop must equal 360° (or equivalently 0°). The common multiple-choice trap: the correct answer is 360°, not 90° or 270°.

MOSFET and BJT

• Q: Describe MOSFET operating regions and how to identify them.

• Approach: Three regions. Cutoff: V_GS < V_T, device is off, no drain current. Triode (linear): V_GS > V_T and V_DS < V_GS - V_T, device acts as a voltage-controlled resistor. Saturation: V_GS > V_T and V_DS ≥ V_GS - V_T, drain current is approximately constant and set by V_GS alone (I_D ≈ (μn·Cox·W/2L)·(V_GS - V_T)²).

• Q: Draw a CMOS inverter and explain its DC transfer characteristic.

• Approach: PMOS (source at VDD) in series with NMOS (source at GND), gates tied together as input, drains tied as output. When V_in is low: PMOS on, NMOS off, V_out = VDD. When V_in is high: NMOS on, PMOS off, V_out = 0. In the transition region, both devices are on briefly, creating a short-circuit current path — this is why CMOS power dissipation scales with switching frequency.

• Q: Explain the Darlington pair and its advantages.

• Approach: Two BJTs in cascade where the emitter of the first drives the base of the second. The effective current gain is approximately β₁ × β₂. This gives very high input impedance (β² × r_e) and is used in power amplifier output stages and when a high-impedance drive is required from a low-current source.

Current Mirrors

• Q: Why is a cascode current mirror preferred over a simple current mirror?
• Approach: In a simple current mirror, the output current varies with V_DS due to channel-length modulation. A cascode mirror adds a second transistor in series at the output, raising the output impedance from r_o to approximately g_m · r_o² (much higher). This reduces the dependence of output current on V_DS, giving closer-to-ideal current copying. Trade-off: the cascode requires more headroom voltage.

Digital Design Profile Interview Questions

Finite State Machines

• Q: Design a divide-by-3 counter using a Moore FSM. Draw the state diagram and write Verilog.
• Approach: Three states: S0 (00), S1 (01), S2 (10), encoded in 2 flip-flops. Transitions: S0 → S1 → S2 → S0 on every rising clock edge. Set output = 1 only in state S0. The Verilog uses two always blocks: one for state register (non-blocking assignments, clocked), one for combinational next-state and output logic.

module div3 (
  input  clk, rst,
  output reg out
);
  reg [1:0] state, next;
  always @(posedge clk)
    state <= rst ? 2'b00 : next;
  always @(*) begin
    case (state)
      2'b00: begin next = 2'b01; out = 1; end
      2'b01: begin next = 2'b10; out = 0; end
      2'b10: begin next = 2'b00; out = 0; end
      default: begin next = 2'b00; out = 0; end
    endcase
  end
endmodule

• Q: What is the difference between a Moore FSM and a Mealy FSM?
• Approach: Moore: outputs are functions of state only, stable between clock edges. Mealy: outputs are functions of both state and current inputs, can change immediately when inputs change (potential glitch). Mealy machines often require fewer states than an equivalent Moore for the same behavior. TI asks this as a conceptual differentiation; be prepared to give a circuit example of each.

Timing Analysis

• Q: Explain setup time and hold time violations and their consequences.

• Approach: Setup time (t_su): the data input must be stable for at least t_su before the clock edge. If data arrives within this window, the flip-flop may enter a metastable state — a high-impedance, undefined output that resolves unpredictably. Hold time (t_h): data must remain stable for at least t_h after the clock edge. A hold violation corrupts the captured value even if setup was clean. Setup is fixed by reducing clock frequency or shortening the combinational path. Hold is fixed by adding buffer delay.

• Q: A flip-flop has t_CQ = 3 ns, t_setup = 2 ns. What is the minimum clock period for a pipeline stage with 5 ns of combinational logic?

• Approach: T_clk ≥ t_CQ + t_comb + t_setup = 3 + 5 + 2 = 10 ns. Maximum clock frequency = 100 MHz.

Verilog and RTL

• Q: What is the difference between blocking and non-blocking assignments in Verilog?

• Approach: Blocking (=): executes immediately, sequentially within the always block, like software code. Non-blocking (<=): schedules the assignment to take effect at the end of the time step, after all right-hand sides have been evaluated. Use = inside always @(*) combinational blocks. Use <= inside always @(posedge clk) sequential blocks. Mixing them in a clocked block causes data races and non-synthesisable behavior.

• Q: Write a Verilog D flip-flop with active-high synchronous reset.

• Approach:

module dff (
  input  clk, rst, d,
  output reg q
);
  always @(posedge clk)
    q <= rst ? 1'b0 : d;
endmodule

Computer Architecture and DSP

• Q: What is the difference between write-through and write-back cache policies?

• Approach: Write-through: every write operation updates both the cache and main memory simultaneously. Simple to implement; no dirty bit needed. Write-back: writes go to the cache only; main memory is updated when the dirty cache line is evicted. Write-back reduces memory bandwidth at the cost of complexity (needs dirty bit and eviction logic). TI asks this in the context of cache-coherence challenges in multi-core embedded processors.

• Q: State the Nyquist theorem and explain aliasing.

• Approach: The sampling frequency must be at least twice the highest frequency component of the signal (f_s ≥ 2 × f_max). If this condition is violated, higher-frequency components fold back into the baseband and are indistinguishable from lower-frequency signals. This is aliasing. In practice, an anti-aliasing low-pass filter is applied before the ADC to remove components above f_s/2.

Questions That Appear in Both Profiles

Universal Logic Sets and NOT Gate Design

TI tests this as a multiple-choice or quick-whiteboard question in both analog and digital interviews.

• Q: Does the set {AND, OR} form a universal logic set?

• Approach: No. AND and OR together cannot implement NOT. Without NOT, you cannot complete the Boolean algebra needed to implement any arbitrary function. NAND alone is universal. NOR alone is universal. A 2-to-1 MUX alone is also universal.

• Q: Implement a NOT gate using only NAND gates, only NOR gates, and using CMOS transistors.

• Approach (NAND): Connect both inputs of a 2-input NAND gate to the same signal A. Output = NAND(A, A) = NOT(A AND A) = NOT(A).

• Approach (NOR): Connect both inputs of a 2-input NOR gate to signal A. Output = NOR(A, A) = NOT(A OR A) = NOT(A).

• Approach (CMOS): Series-connected PMOS (source at VDD, gate = A) and NMOS (source at GND, gate = A), drains tied as output. When A = 1: NMOS conducts, PMOS cuts off, output = 0. When A = 0: PMOS conducts, NMOS cuts off, output = VDD = 1.

The HR Round

The HR round at TI is shorter and less eliminatory than the technical rounds. Reaching it typically means the offer is near. Three questions come up across placement accounts:

• Q: Why do you prefer the Analog Design profile over Digital Design (or vice versa)?

• Approach: Be specific. “I prefer analog because I find the intuition-first reasoning in RC transient analysis more satisfying than simulation results” reads as genuine. Generic answers about “liking both” do not.

• Q: Where do you see yourself in two to three years?

• Approach: Align with IC design or embedded systems — TI’s actual domain. Saying “I want to move to software in two years” is a red flag in a semiconductor company’s core-profile interview.

• Q: How do you see your academic projects connecting to TI’s work?

• Approach: Reference something specific: the VLSI project that involved standard-cell synthesis, the analog filter design that required Cadence Virtuoso, or the FPGA project that used timing constraints. Vague answers about “wanting to apply engineering skills” do not answer the question.

Samsung conducts comparable circuit-theory interview rounds for its semiconductor and display hardware profiles. The Samsung recruitment process for freshers is a useful second data point if you are targeting multiple hardware-company drives in the same season.

ECE students exploring the full spread of hiring options, from core hardware profiles like TI’s to software and IT roles, can review IT jobs for freshers for a comparison of the two tracks.

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The divide-by-3 counter and Verilog RTL questions in TI’s digital profile are testing something beyond syntax: the ability to reason about deterministic state machines and timing constraints. Those same instincts apply when building the control logic for an AI inference pipeline on embedded hardware. TinkerLLM covers the LLM API and tool-calling layer at ₹299 (the software half that pairs with the hardware logic TI already tests). A 3-hour session on the platform gives you the API vocabulary before your next technical round.